The chip industry needs to shift its investment from manufacturing to design, believes Synopsys, making the reuse of IP a reality. Chris report

Fabs around the world are running on empty, waiting for the next killer application for big chips to come along. Unfortunately, figures show that many designs are failing to demand much more silicon area than they do today, let alone scrape the edges of the reticle.

Project pressures mean that ambitious system-on-chip designs are not appearing quickly enough, and a design infrastructure intended for design from scratch makes it difficult to justify reusing intellectual property (IP).

It's not a pretty sight, is it? Not so, says Aart de Geus, chairman and CEO of Synopsys, the design tools company, who is looking for a bonanza in his own business.

"The health of the industry is built on how quickly you can get round the loop," he said. "We are not capable of designing the products quickly enough. But the optimistic view is that there is a massive opportunity.

"What the semiconductor industry should do is move billions of dollars from production into design."

That the money in silicon should move the way of design has become a popular mantra among EDA company executives. Against the $120bn behemoth that is semiconductor manufacture, the $2.5bn to $3bn that is spent on EDA is not an impressive figure. Of course, you have to add the money that funds electronic design using those tools, but it still seems small compared with the cash ploughed into manufacture.

He and his colleagues point to over-investment in manufacturing technology - a holdover from the fact that, among many semiconductor companies, it is the process people and not the designers who have risen to the top. Perhaps we should expect this kind of investment skew given that process technology is expensive.

But with the silicon glut expected to continue, perhaps investment in manufacturing has now reached its natural limit.

The problem facing these companies is that their differentiation is rapidly disappearing in the face of a new generation of designs.

"The industry is becoming much more horizontal," he said. "If there is a single word to capture it, it's convergence. The phrase system-on-chip is appropriate for this new generation of design. You have to put computing and communications on-chip. That implies one has to have access to those different domains."

In the same way that the PC industry drove the migration from 1 micro m to 0.35 micro m processes, there are new devices that will help pay for the next moves, such as digital TV, third-generation (3G) cellular telephony and Internet access devices.

"Digital TV will be driven by the Olympics; 3G is about one year behind. That means the chips have to be designed in 1999, and that's happening," he said.

The cost restrictions of those designs means that semiconductor producers have to incorporate new skills and techniques, and quickly: you may be king of the hill in microprocessors but have no DVD. Therefore, IP that is mobile enough will have a very high value if you can assemble it on to a chip.

"There is IP and there is IP. IP which is extremely valuable: that is the central magnet. For example, the DSP core from Texas Instruments - they will want to attract IP around that.

"This is fundamentally a question of what is your differentiation. Promote that maximally and then glue the rest around it. ARM has been miraculously successful in that respect. The challenge is that a lot of the intellectual property needed is often in-house."

Making internal reuse happen is not just a technical problem, but one of ensuring that reusing a piece of IP does not take longer than designing it from scratch. That means designing blocks with a view to reuse.

"When we built our first major IP, we went overboard in making it flexible. It made it extremely difficult to use," he said. "Some of the options were like the choke on an old car. You were never sure whether it should be in or out when you started the car. We had 60 of those in the PCI core.

"Finding the right balance comes with experience. We failed miserably on the first one, so we decided on a set of parameters that were usable."

Many systems houses have the opposite problem to an IP supplier: the core may not be flexible at all. But under pressure from top-level management, they still have to be distributed and supported.

"Economically, the incentive for reuse is a global one but the incentive for success is a local one. People agree that design-for- reuse is a good idea. The issue is that if you are engaged in design, you are involved with the time it takes to create the first issue.

"When there is a problem with achieving both, do you give up reuse or the time to the first issue?

"You have the problem of corporate perspective versus bottom-up reality. It's a lot easier to stop smoking tomorrow than it is today. And six months later, nothing much has happened.

"With any fundamental changes, it's as much a cultural management change as a technical change. And change management is difficult, no matter what. Companies tend to go for extremes. First it's a top-down directive, then they go to 'it's too difficult'. Then it's a case of learning which compromises work.

"We participate with a number of companies, help move over companies to do that."

Even though internal company politics remain a huge problem, it does not mean that EDA suppliers are off the hook. You can split the EDA world into four, currently discrete, domains: front-end design which takes in synthesis; the back-end design processes dominated by place- and-route; front-end verification such as simulation; and back-end analysis, which concentrates on low-level electrical effects. In at least three of the main chip design domains, major changes are needed.

"The single biggest problem is the interaction between the logical and physical level. It applies less to the IP itself than the circumstances in which it is used," he said.

The interaction is worst between synthesis and layout. Because synthesis works purely at the logical level, it can make decisions which affect the way the transistors are laid out in such a way that the design cannot meet the timing necessary to function correctly.

But that is not the only issue. Below 0.25 micro m, parasitic electrical effects such as crosstalk and electromigration will have a huge effect not only on timing but on whether the device will work at all.

"The effects are compounded by the problem that there are many of them on a chip. You can diagnose all of your crosstalk problems today, but they have to be designed out automatically," he said.

The only way to do that is to drive the routing process using crosstalk analysis: "Routing will be tied to analysis, placement to synthesis."

Electromigration poses more difficult problems. Even extensive work with low-level placement and routing tools may not be enough to remove electromigration issues if the design needs a certain combination of transistors to achieve timing. The only way to solve it is to move the analysis results closer to the beginning of the design process and get the synthesis tool to remove the problem by changing the logic.

"Power-related issues will drive design in the future. Analysis and verification always precedes automation. It is more measurable, but not at the level where it can be optimised automatically.

"At each stage, there is a set of revolutionary decisions you need to make. You need both a physical and mental retooling, or retraining, in how you do design." The question of revolution versus evolution in EDA is one that drove the recent takeover battle between Mentor Graphics and Quickturn.

Realising that simulation time continues to increase exponentially, both companies decided that the product needed would be a faster simulator, in this case, using hardware to accelerate the process. The result was a fight for control over a market that analysts continue to regard as lacklustre.

The alternative is a revolution in verification similar to the shift from schematic capture to RTL design using synthesis tools during the move from 1 to 0.5 micro m processes.

Formal verification attempts to demonstrate that a design will work without running simulation vectors but by proving that it is correct. Coupled with static timing analysis, it can reduce dramatically the amount of computer time needed to verify a design. But it demands that designers get to grips with new approaches to design and verification.

"It depends on how disciplined they are. If they use synthesis, they have already decoupled timing and functionality."